Method for Semiconductor Device Fabrication with Improved Source Drain Epitaxy

A semiconductor structure, comprising:

• a substrate;
• fins extending from the substrate;
• first gate structures and second gate structures over the substrate and engaging the fins, the first gate structures having a greater pitch than the second gate structures;
• third epitaxial semiconductor features adjacent the first gate structures;
• and
• fourth epitaxial semiconductor features adjacent the second gate structures, wherein the third and fourth epitaxial semiconductor features are partially embedded in the fins and raised above a top surface of the fins, wherein a first depth of the third epitaxial semiconductor features embedded into the fins is greater than a second depth of the fourth epitaxial semiconductor features embedded into the fins.

A method, comprising:

• receiving a structure having a substrate, fins extending from the substrate, and first and second pluralities of gate structures engaging the fins, the first plurality of gate structures having a larger pitch than the second plurality of gate structures;
• forming gate spacers on sidewalls of the first and second pluralities of gate structures;
• depositing a first dielectric layer over the substrate, the fins, the first and second pluralities of gate structures, and the gate spacers;
• etching the first dielectric layer to remove the first dielectric layer except that a portion of the first dielectric layer is kept over sidewalls of the first and second pluralities of gate structures, wherein the portion of the first dielectric layer is thicker over the sidewalls of the second plurality of gate structures than over the sidewalls of the first plurality of gate structures;
• after the etching of the first dielectric layer, etching the fins to form third and fourth pluralities of recesses adjacent the first and second pluralities of gate structures, respectively, wherein the third plurality of recesses is deeper than the fourth plurality of recesses;
• and
• epitaxially growing fifth and sixth pluralities of semiconductor features in the third and fourth pluralities of recesses, respectively.