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US 2017/0373172 A1Published application
Semiconductor device and manufacturing method thereof
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorShunpei YAMAZAKI
Life of this patent
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Abstract
An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
Claims9
(canceled)
A semiconductor device comprising a pixel portion, and a connection portion with a FPC,
- the pixel portion comprising:
- a first conductive layer;
- a first insulating layer over the first conductive layer;
- an oxide semiconductor layer over the first insulating layer;
- a second conductive layer electrically connected to the oxide semiconductor layer;
- a third conductive layer electrically connected to the oxide semiconductor layer;
- a second insulating layer over the oxide semiconductor layer, the second conductive layer, and the third conductive layer;
- and
- a pixel electrode over the second insulating layer and electrically connected to the third conductive layer,
- wherein the first conductive layer and the second conductive layer cross each other in a cross shape and overlap each other in a first region,
- wherein the first region overlaps a first transparent conductive layer,
- wherein a gate wiring and a gate electrode of a transistor are formed from the first conductive layer,
- wherein the first conductive layer comprises a region overlapping the oxide semiconductor layer with the first insulating layer interposed therebetween,
- wherein a source wiring and one of a source electrode and a drain electrode of the transistor are formed from the second conductive layer, and
- wherein the other of the source electrode and the drain electrode of the transistor is formed from the third conductive layer,
- the connection portion comprising:
- a fourth conductive layer formed from a same layer as the first conductive layer and comprises a same material as the first conductive layer;
- a fifth conductive layer formed from a same layer as the second conductive layer and comprises a same material as the second conductive layer;
- and
- a second transparent conductive layer comprising a same material as the first transparent conductive layer,
- wherein an electrode or a wiring formed from the second transparent conductive layer is electrically connecting to the FPC,
- wherein the fifth conductive layer comprises a region in contact with a top surface of the second transparent conductive layer, and
- wherein the fourth conductive layer comprises a region in contact with a top surface of the fifth conductive layer.
20 more elements
A semiconductor device comprising a pixel portion, and a connection portion with a FPC,
- the pixel portion comprising:
- a first conductive layer;
- a first insulating layer over the first conductive layer;
- an oxide semiconductor layer over the first insulating layer;
- a second conductive layer electrically connected to the oxide semiconductor layer;
- a third conductive layer electrically connected to the oxide semiconductor layer;
- a second insulating layer over the oxide semiconductor layer, the second conductive layer, and the third conductive layer;
- a pixel electrode over the second insulating layer and electrically connected to the third conductive layer;
- and
- a first transparent conductive layer comprising a same material as the pixel electrode,
- wherein the first conductive layer and the second conductive layer cross each other in a cross shape and overlap each other in a first region,
- wherein the first region overlaps the first transparent conductive layer, wherein a gate wiring and a gate electrode of a transistor are formed from the first conductive layer,
- wherein the first conductive layer comprises a region overlapping the oxide semiconductor layer with the first insulating layer interposed therebetween,
- wherein a source wiring and one of a source electrode and a drain electrode of the transistor are formed from the second conductive layer, and
- wherein the other of the source electrode and the drain electrode of the transistor is formed from the third conductive layer,
- the connection portion comprising:
- a fourth conductive layer formed from a same layer as the first conductive layer and comprises a same material as the first conductive layer;
- a fifth conductive layer formed from a same layer as the second conductive layer and comprises a same material as the second conductive layer;
- and
- a second transparent conductive layer comprising a same material as the first transparent conductive layer,
- wherein an electrode or a wiring formed from the second transparent conductive layer is electrically connecting to the FPC,
- wherein the fifth conductive layer comprises a region in contact with a top surface of the second transparent conductive layer, and
- wherein the fourth conductive layer comprises a region in contact with a top surface of the fifth conductive layer.
20 more elements
Dependencies are inferred from the claim text.