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US 2017/0373166 A1Published application
Vertical transport field effect transistor with precise gate length definition
AssigneeInternational Business Machines Corporation
InventorsMarc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
Life of this patent
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Abstract
Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.
Claims11
-10. (canceled)
A method of forming a gate stack for a semiconductor device, the method comprising:
- forming a vertical fin on a substrate, the vertical fin having an upper portion and a bottom portion, wherein the upper portion of the vertical fin has a recessed portion on sides of the upper portion;
- and
- forming the gate stack in the recessed portion of the upper portion of the vertical fin, such that the gate stack is on the sides of the upper portion but not above the upper portion of the vertical fin.
A method of forming a gate stack for a semiconductor device, the method comprising:
- forming a vertical fin on a substrate, the vertical fin having an upper portion and a bottom portion;
- forming a recessed portion in the upper portion of the vertical fin such that the recessed portion is on sides of the upper portion;
- and
- forming the gate stack in the recessed portion of the upper portion of the vertical fin, such that the gate stack is on the sides of the upper portion but not above the upper portion of the vertical fin, wherein a gate length is predefined by the recessed portion.
1 more element
Dependencies are inferred from the claim text.