2D Material Super Capacitors
AssigneeSynopsys, Inc.
InventorsJamil Kawa, Victor Moroz
Life of this patent
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Abstract
Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide. In an embodiment a capacitor device includes 10,000 layers of interleaved graphene separated by 9,999 layers of HfO. Odd layers of the graphene are electrically connected to a first terminal and even layers of graphene are electrically connected to a second terminal of the capacitor device.
Claims21
A method of simulating the fabrication process flow of a capacitor device on a substrate having formed therein a plurality of active devices, a plurality of conductive interconnect layers formed above the substrate, and including a top interconnect layer having first and second conductive pads, comprising:
- simulating forming a first capacitor above the top interconnect layer, including:
- simulating forming a first conductive 2D material electrode;
- simulating forming a first dielectric layer immediately overlying the first 2D material electrode;
- and
- simulating forming a second conductive 2D material electrode immediately overlying the first dielectric layer;
- simulating forming a second capacitor including:
- simulating forming a second dielectric layer immediately overlying the second 2D material electrode;
- and
- simulating forming a third conductive 2D material electrode immediately overlying the second dielectric layer;
- and
- simulating connecting the first and third conductive 2D material electrode to the first conductive pad;
- simulating connecting the second conductive 2D material electrode to the second conductive pad;
- and
- outputting a database describing the structure resulting from the fabrication process flow.
A method of simulating an integrated circuit, including a capacitor device, to extract parameters of the capacitor device, comprising:
- providing a computer readable storage medium, having stored thereon in a non-transitory manner a computer readable description of the structure of a capacitor device, wherein the capacitor device comprises:
- a first set of conductive layers all connected to a first terminal of the capacitor and each comprising a 2D material, and
- a second set of conductive layers all connected to a second terminal of the capacitor and each comprising a 2D material,
- wherein the layers in the first set of conductive layers are interleaved with the layers in the second set of conductive layers and separated from the layers in the second set of conductive layers by intervening layers of dielectric material,
- wherein the first and second sets of conductive layers together include at least 5,000 conductive layers, and
- wherein the multilayer capacitor is integrated in an integrated circuit;
- and
- extracting parameters of the capacitor device from the structure.
An article of manufacture, comprising a computer readable storage medium, having stored thereon in a non-transitory manner a computer readable definition of shapes for a photolithographic mask set for defining features to be formed on an integrated circuit using the mask set, wherein the features define a capacitor device comprising a plurality of stacked capacitors, each capacitor comprising:
- a first conductive 2D material layer, having topside and bottomside surface;
- a dielectric layer immediately overlying the topside surface of the first 2D material layer;
- and
- a second conductive 2D material layer, the second 2D material electrode having topside and bottomside surface, the bottomside of the second 2D material layer immediately overlying the first dielectric layer,
- wherein the first and the second layers are opposite electrodes of a first capacitor,
- wherein the first layer is also an electrode of a second capacitor,
- wherein the second layer is also an electrode of a third capacitor, and
- wherein the first 2D material layer, the first dielectric layer, and the second 2D material layer have a total thickness of less than 3 nm.
An article of manufacture, comprising a computer readable storage medium, having stored thereon in a non-transitory manner a database which identifies a macrocell when interpreted by a computer system, the macrocell identifying shapes for a photolithographic mask set for defining features to be formed on an integrated circuit using the mask set, wherein the features define a capacitor device comprising a plurality of stacked capacitors, each capacitor comprising:
- a first conductive 2D material layer, having topside and bottomside surface;
- a dielectric layer immediately overlying the topside surface of the first 2D material layer;
- and
- a second conductive 2D material layer, the second 2D material electrode having topside and bottomside surface, the bottomside of the second 2D material layer immediately overlying the first dielectric layer,
- wherein the first and the second layers are opposite electrodes of a first capacitor,
- wherein the first layer is also an electrode of a second capacitor,
- wherein the second layer is also an electrode of a third capacitor, and
- wherein the first 2D material layer, the first dielectric layer, and the second 2D material layer have a total thickness of less than 3 nm.
A method for laying out an integrated circuit device, the device to include a capacitor device which includes a plurality of stacked capacitors, comprising:
- laying out first mask layer shapes which when applied to the device form odd numbered 2D material electrodes;
- laying out second mask layer shapes which when applied to the device form odd numbered dielectric layers, each odd numbered dielectric layer immediately overlying one of the odd numbered 2D material electrodes;
- laying out third mask layer shapes which when applied to the device form even numbered 2D material electrodes, each even numbered 2D material electrode immediately overlying one of the odd numbered dielectric layers;
- laying out fourth mask layer shapes which when applied to the device form even numbered dielectric layers, each even numbered dielectric layer immediately overlying one of the even numbered 2D material electrodes,
- wherein the total thickness of one of the odd numbered 2D material electrodes, one of the odd numbered dielectric layers, and one of the even numbered 2D material electrodes is less than 3 nm.
Dependencies are inferred from the claim text.