Semiconductor chip and multi-chip package using thereof
AssigneeNanya Technology Corporation
InventorPO CHUN LIN
Life of this patent
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Abstract
The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking aligmnent and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side.
Claims23
A semiconductor chip, comprising:
- a semiconductor substrate having a first side and a second side;
- a conductive through plug extending through the semiconductor substrate from the first side to the second side;
- a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side, wherein the non-through plug includes an exposed surface that is coplanar to the first side;
- a first conductive member on the first side;
- and
- wherein the conductive through plug electrically couples the first conductive member, while the non-through plug does not electrically couple the first conductive member.
A chip package comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip comprises:
- a semiconductor substrate having a first side and a second side;
- a conductive through plug extending through the semiconductor substrate from the first side to the second side;
- and
- a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side, wherein the non-through plug includes an exposed surface that is coplanar to the first side;
- wherein the second semiconductor chip is adjacent to the first semiconductor chip, and the conductive through plug is coupled to a conductive member of the second semiconductor chip, while the non-through plug is not electrically coupled to the conductive member of the second semiconductor chip;
- wherein the non-through plug is aligned with an alignment pattern on the second semiconductor chip.
A method for manufacturing a semiconductor chip, comprising the steps of:
- preparing a semiconductor substrate having a first side and a second side;
- forming a first hole and a second hole in the semiconductor substrate, wherein the first hole has a first depth and the second hole has a second depth smaller than the first depth;
- and
- forming a conductive through plug in the first hole and a non-through plug in the second hole, wherein the conductive through plug extends through the semiconductor substrate from the first side to the second side, while the non-through plug extends from the first side to an internal plane without extending through the second side.
Dependencies are inferred from the claim text.