US 2017/0373000 A1Published application

Interconnects having hybrid metallization

AssigneeGlobalfoundries Inc.

InventorsXunyuan Zhang, Ruilong Xie

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Abstract

Disclosed are methods of forming integrated circuit (IC) structures with hybrid metallization interconnects. A dual damascene process is performed to form trenches in an upper portion of a dielectric layer and contact holes that extend from the trenches to a gate electrode and to contact plugs on source/drain regions. A first metal is deposited into the contact holes by electroless deposition and a second metal is then deposited. Alternatively, a single damascene process is performed to form a first contact hole through a dielectric layer to a gate electrode and a first metal is deposited therein by electroless deposition. Next, a dual damascene process is performed to form trenches in an upper portion of the dielectric layer, including a trench that traverses the first contact hole, and to form second contact holes that extend from the trenches to contact plugs on source/drain regions. A second metal is then deposited.

Claims20

Dependent claims

A method comprising:

forming a field effect transistor comprising:
source/drain regions;
a channel region positioned laterally between the source/drain regions;
a gate electrode above the channel region;
and
contact plugs above the source/drain regions and isolated from the gate electrode by a gate sidewall spacer;
forming a dielectric layer above the field effect transistor, the dielectric layer having a bottom surface and a top surface opposite and essentially parallel to the bottom surface, the bottom surface being immediately adjacent to top surfaces of the contact plugs and extending laterally over the gate sidewall spacer and the gate electrode;
performing a dual damascene process to form trenches in an upper portion of the dielectric layer and contact holes extending vertically from the trenches through a lower portion of the dielectric layer, the contact holes comprising at least:
a first contact hole extending vertically to the bottom surface of the dielectric layer so as to be adjacent to the gate electrode of the field effect transistor;
and,
a second contact hole extending vertically to the bottom surface of the dielectric layer so as to be immediately adjacent to a contact plug on a source/drain region of the field effect transistor;
essentially simultaneously depositing a first metal into the contact holes using an electroless deposition process;
and
after the depositing of the first metal, depositing a second metal to fill the trenches, the second metal being different from the first metal.

11 more elements

A method comprising:

forming a field effect transistor comprising:
source/drain regions;
a channel region positioned laterally between the source/drain regions;
a gate electrode above the channel region;
and
contact plugs above the source/drain regions and isolated from the gate electrode by a gate sidewall spacer;
forming a dielectric layer above the field effect transistor, the dielectric layer having a bottom surface and a top surface opposite and essentially parallel to the bottom surface, the bottom surface being immediately adjacent to top surfaces of the contact plugs and extending laterally over the gate sidewall spacer and the gate electrode;
performing a dual damascene process to form trenches in an upper portion of the dielectric layer and contact holes extending vertically from the trenches through a lower portion of the dielectric layer, the contact holes comprising at least:
a first contact hole extending vertically to the bottom surface of the dielectric layer so as to be adjacent to the gate electrode of the field effect transistor;
and,
a second contact hole extending vertically to the bottom surface of the dielectric layer so as to be immediately adjacent to a contact plug on a source/drain region of the field effect transistor;
essentially simultaneously depositing a first metal into the contact holes using an electroless deposition process;
depositing a conformal barrier layer;
and
depositing a second metal to fill the trenches, the second metal being different from the first metal and the conformal barrier layer physically separating the second metal from the dielectric layer and the first metal.

12 more elements

An integrated circuit structure comprising:

a field effect transistor comprising source/drain regions, a channel region between the source/drain regions and a gate electrode on the channel region and a gate sidewall spacer laterally surrounding the gate electrode;
contact plugs on the source/drain regions;
a dielectric layer above the field effect transistor, the dielectric layer having a bottom surface and a top surface opposite and essentially parallel to the bottom surface, the bottom surface being immediately adjacent to top surfaces of the contact plugs and extending laterally over the gate sidewall spacer and the gate electrode;
metal wires in an upper portion of the dielectric layer;
contacts extending vertically from the metal wires through a lower portion of the dielectric layer to the bottom surface of the dielectric layer, the contacts comprising at least:
a first contact extending vertically through the lower portion of the dielectric layer to the bottom surface of the dielectric layer so as to be adjacent to the gate electrode;
and,
a second contact extending vertically through the lower portion of the dielectric layer to the bottom surface of the dielectric layer so as to be immediately adjacent to a contact plug,
the contacts each comprising at least a first metal,
the metal wires comprising at least a second metal that is different from the first metal, and
the second metal being physically separated from the first metal by a conformal barrier layer.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/701,480Filed 12 Sep 2017
Priority: 27 Jun 2016
Published: 28 Dec 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

H10W 20/43
Characterised by their conductive parts: layouts of interconnections
H10W 20/033
Of conductive barrier, adhesion or liner layers: in openings in dielectrics
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 20/057
By filling conductive material into holes, grooves or trenches: by selectively depositing, e.g. by using selective CVD or plating