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US 2017/0372995 A1Published application
Fan-out semiconductor package
AssigneeSamsung Electro-Mechanics Co., Ltd.
InventorsSung Han KIM, Masazumi AMAGAI, Ju Ho KIM, Tae Sung JEONG
Life of this patent
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Abstract
A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.
Claims23
A fan-out semiconductor package comprising:
- a first interconnection member having a through-hole;
- a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface;
- an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip;
- a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip;
- and
- a connection terminal disposed on the second interconnection member,
- wherein the first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pad of the semiconductor chip, and
- the connection pad and the connection terminal are electrically connected by an electrical pathway in the second interconnection member, the electrical pathway including a first via connected to the connection pad and having a central axis disposed in an inner region of a connection terminal pad connected to the connection terminal and a second via connected to a via pad formed on the layer on which the connection terminal pad is disposed and having a central axis disposed in an outer region of the connection terminal pad.
5 more elements
A fan-out semiconductor package comprising:
- a first interconnection member having a through-hole;
- a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface;
- an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip;
- a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip;
- and
- a connection terminal disposed on the second interconnection member,
- wherein the first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pad of the semiconductor chip, and
- the connection pad and the connection terminal are electrically connected by an electrical pathway in the second interconnection member, the electrical pathway including a first via connected to the connection pad and a second via connected to a via pad formed on the layer on which a connection terminal pad is disposed, a central axis of the first via being displaced laterally from a central axis of the second via.
5 more elements
Dependencies are inferred from the claim text.