Sharing global route topologies in detailed routing

A method for creating layouts of integrated circuits, the method comprising:

• accessing, using a processor, an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit, the initial layout created by a global router based on the gate level design description, the initial layout of wires specifying connections between regions on the integrated circuit;
• accessing, using the processor, a second layout that specifies, for each net, detailed routing information including connections between specific wires in the regions of the integrated circuit, the second layout created by a detailed router based on the initial layout and including a failing net that is missing a connection in the second layout between two of the regions;
• generating a list of nets with a same source region and target region in the initial layout as the failing net;
• selecting a net in the list of nets;
• rerouting the failing net over the selected net, the rerouting comprising the global router updating the initial layout and the detailed router updating the second layout;
• and
• updating the congestion related metric for each net in response to the global router updating the initial layout.