US 2017/0371995 A1 · STANDARD CELL ARCHITECTURE FOR DIFFUSION BASED ON FIN COUNT

Abstract

Disclosed systems and methods pertain to finfet based integrated circuits designed with logic cell architectures which support multiple diffusion regions for n-type and p-type diffusions. Different diffusion regions of each logic cell can have different widths or fin counts. Abutting two logic cells is enabled based on like fin counts for corresponding p-diffusion regions and n-diffusion regions of the two logic cells. Diffusion fills are used at common edges between the two logic cells for extending lengths of diffusion, based on the like fin counts. The logic cell architectures support via redundancy and the ability to selectively control threshold voltages of different logic cells with implant tailoring. Half-row height cells can be interleaved with standard full-row height cells.

Claims36

Dependent claims

A method of designing an integrated circuit with finfet based logic cells, the method comprising forming at least a first logic cell with at least one of:

two or more p-diffusion regions;
or
two or more n-diffusion regions.

A method of designing an integrated circuit with finfet based logic cells, the method comprising:

placing a first logic cell having a first logic cell boundary adjacent to a second logic cell having a second logic cell boundary, wherein the first logic cell boundary and the second logic cell boundary have a common edge,
wherein the first logic cell comprises at least one pfet formed on a first p-diffusion region with a first fin count and at least one nfet formed on a first n-diffusion region with a second fin count, and
wherein the second logic cell comprises at least one pfet formed on a second p-diffusion region with the first fin count and at least one nfet formed on the second n-diffusion region with the second fin count;
and
forming at least one of:
a first p-diffusion fill traversing the common edge and joining the first p-diffusion region of the first logic cell and the second p-diffusion region of the second logic cell;
or
a first n-diffusion fill traversing the common edge and joining the first n-diffusion region of the first logic cell and the second n-diffusion region of the second logic cell.

5 more elements

A method of designing an integrated circuit with finfet based logic cells, the method comprising:

forming a first full row comprising at least a first full-row height logic cell, wherein the first full-row height logic cell comprises at least one of two or more p-diffusion regions or two or more n-diffusion regions;
forming a second full row adjacent to the first full row, the second full row comprising at least a second full-row height logic cell, wherein the second full-row height logic cell comprises at least one of two or more p-diffusion regions or two or more n-diffusion regions;
and
interspersing one or more sub-rows between the first full row and the second full row, wherein at least a first sub-row of the one or more sub-rows comprises a first half-row height logic cell comprising at least one p-diffusion region and at least one n-diffusion region, wherein at least one of:
the at least one p-diffusion region of the first half-row height logic cell is adjacent to one of the two or more p-diffusion regions of the first full-row height logic cell or the second full-row height logic cell, or
the at least one n-diffusion region of the first half-row height logic cell is adjacent to one of the two or more n-diffusion regions of the first full-row height logic cell or the second full-row height logic cell.

3 more elements

Dependencies are inferred from the claim text.

Standard cell architecture for diffusion based on fin count

Life of this patent

Standard cell architecture for diffusion based on fin count

Life of this patent

Abstract

Claims36