Optimizing the layout of circuits based on multiple design constraints
AssigneeInternational Business Machines Corporation
InventorsRobert Louis FRANCH, George Diedrich GRISTEDE, Matthew Mantell ZIEGLER
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AssigneeInternational Business Machines Corporation
InventorsRobert Louis FRANCH, George Diedrich GRISTEDE, Matthew Mantell ZIEGLER
Estimating the term…
Disclosed is a system, computer program product, and method for performing logic, physical synthesis, and post-route optimization. The method begins with identifying a plurality of groups of paths in a circuit by a unique criteria. The unique criteria is any one of a netlist regular expression, a cell topology regular expression, a physical structure, or a combination thereof. An optimization process is performed on the design and is repeated until the cumulative histogram corresponds to the reference histogram within a threshold. The histogram optimization on the group of paths to make the cumulative histogram correspond to the reference cumulative histogram can be adjusted to account for timing, power, yield, or a combination thereof. After a first group of paths has been optimized, the process can be repeated for other groups of paths. The histogram optimization performed on each group of paths is merged into overall histogram optimization design.
A method for performing histogram optimization on a design, the method comprising:
A system for performing histogram optimization on a design, the system comprising:
A computer program product for performing histogram optimization on a design, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to:
Dependencies are inferred from the claim text.