Targeted per-line operations for remote scope promotion
AssigneeAdvanced Micro Devices, Inc.
InventorsJohnathan R. Alsop, Bradford Beckmann
Life of this patent
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Abstract
A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the one or more first caches, and a plurality of second lock tables associated with the plurality of second caches. The first and second lock tables indicate locking states of addresses of cache lines in the corresponding first and second caches on a per-line basis.
Claims20
An apparatus comprising:
- at least one first lock table associated with at least one first cache;
- and
- at least one processing unit, wherein each processing unit comprises:
- a plurality of compute units for concurrently executing work-groups of work items;
- a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the at least one first cache;
- and
- a plurality of second lock tables associated with the plurality of second caches, wherein the first and second lock tables indicate locking states of addresses of cache lines in the corresponding first and second caches on a per-line basis.
A method, comprising:
- synchronizing threads executed by first processing elements in a first compute unit using a first cache associated with the first compute unit;
- synchronizing threads executed by second processing elements in a second compute unit using a second cache associated with the second compute unit;
- and
- selectively synchronizing, on a per-line basis, threads executed by the first and second processing elements using a third cache based on locking states of addresses of cache lines in the first and second caches, wherein the locking states are indicated by first and second lock tables for the first and second caches, and wherein the third cache is at a higher level in a cache hierarchy that includes the first and second caches.
A non-transitory computer readable storage medium embodying a set of executable instructions, the set of executable instructions to manipulate a computer system to perform a portion of a process to fabricate at least part of a processor, the processor comprising:
- at least one first lock table associated with at least one first cache;
- and
- at least one processing unit, wherein each processing unit comprises:
- a plurality of compute units for concurrently executing work-groups of work items;
- a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the at least one first cache;
- and
- a plurality of second lock tables associated with the plurality of second caches, wherein the first and second lock tables indicate locking states of addresses of cache lines in the corresponding first and second caches on a per-line basis.
Dependencies are inferred from the claim text.