Pin control method and device

A pin control device, applied to a first chip comprising a sleep pin connected with a wakeup pin on a second chip, a RTS pin connected with a CTS pin on the second chip, a RXD pin connected with a TXD pin on the second chip, the device comprising:

• a processor;
• and
• a memory configured to store instructions executable by the processor;
• wherein the processor is configured to:
• receive, by the sleep pin, a data sending signal sent by the second chip;
• set the RTS pin into an effective state according to the data sending signal;
• receive, by the RXD pin, data sent by the second chip, the RXD pin being in the effective state when the RTS pin is in the effective state;
• receive, by the sleep pin, a transmission completion signal sent by the second chip;
• set the RTS pin into an ineffective state according to the transmission completion signal;
• and
• determine, according to a current running condition, whether to enter a sleep state.

A pin control device, applied to a second chip comprising a wakeup pin connected with a sleep pin on a first chip, a CTS pin connected with a RTS pin on the first chip, a TXD pin connected with a RXD pin on the first chip, the device comprising:

• a processor;
• and
• a memory configured to store instructions executable by the processor;
• wherein the processor is configured to:
• send, by the wakeup pin, a data sending signal to the first chip;
• detect, by the CTS pin, whether the RTS pin is in an effective state;
• send, by the TXD pin, data to the first chip if the RTS pin is in the effective state;
• and
• when data transmission is completed, send, by the wakeup pin, a transmission completion signal to the first chip for:
• setting the RTS pin into an ineffective state according to the transmission completion signal and
• determining, according to a current running condition, whether to enter a sleep state.