Systems, methods and devices for standby power entry without latency tolerance information
AssigneeIntel Corporation
InventorsBarnes Cooper, Neil W. Songer
Life of this patent
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Abstract
Standby power entry can be performed without latency tolerance information. The embodiments disclosed herein enable a power delivery system of a computing system to enter the requested low power state while ignoring any latency tolerance information throughout the platform. For example, an operating system (OS) can request a Forced Cx state (also known as a Forced C state), such as a Forced C10 state, allowing the system to ignore any latency tolerance information throughout the platform. This Forced Cx state can be used as a test mechanism to determine if a problematic device or integrated circuit is blocking entry into the low power state.
Claims25
A north power controller for transitioning to a low power state comprising:
- a processor configured to:
- receive a request to transition a computing system to the low power state without latency tolerance;
- send a power management message to a south power controller indicating a first time when the north power controller will be ready to exit the low power state and an indication to operate without latency tolerance;
- receive a response from the south power controller confirming the request to operate without latency tolerance and a second time until the south power controller will be ready to exit the low power state;
- transition to the low power state;
- and
- transition to an active state on or before the earlier of the first time and the second time occurs.
An apparatus of a south power controller, the apparatus comprising:
- a processor configured to:
- receive a power management message from a north power controller indicating a first time when the north power controller will exit a low power state and an indication to operate without latency tolerance;
- generate a response to the north power controller confirming the request to operate without latency tolerance and a second time when the south power controller will exit the low power state;
- assert a SLP_S0# signal;
- and
- transition to the low power state.
A computer program product comprising a computer-readable storage medium that stores instructions for execution by a processor to perform power management operations of a system on a chip (SoC), the operations, when executed by the processor, to perform a method, the method comprising:
- receiving a request to transition the SoC to a low power state with an indicator to ignore latency tolerance;
- sending a power management message to a south power controller indicating a first time when the north power controller will be ready for the low power state and an indication to operate without latency tolerance;
- receiving a response from the south power controller confirming the request to operate without latency tolerance and a second time until the south power controller will be ready for the low power state;
- and
- on or after a later of the first and the second time occurs, transitioning to the low power state.
Dependencies are inferred from the claim text.