Processor Having Accelerated User Responsiveness In Constrained Environment
AssigneeIntel Corporation
InventorsEfraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
Life of this patent
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Abstract
In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
Claims22
A processor comprising:
- at least one core to execute instructions;
- and
- a power controller coupled to the at least one core, the power controller including a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state.
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- causing at least one core of a processor to exit a low power state, responsive to identification of a responsiveness workload to be executed;
- causing the at least one core to exit the idle state and directly enter into a maximum performance state for a first duration;
- after the first duration, causing the at least one core to enter into a second performance state until a first budget is consumed, the second performance state greater than a sustained performance state;
- and
- after the first budget is consumed, causing the at least one core to enter into the sustained performance state.
A system comprising:
- a processor including a plurality of cores and a power controller, responsive to identification of a user workload, to cause at least a first core of the plurality of cores to exit an idle state and enter into a maximum performance state for a first time duration indicated in a configuration register, thereafter enter into a plurality of intermediate power states according to an exponential decay function, and thereafter enter into a sustained performance state;
- and
- a dynamic random access memory coupled to the processor.
Dependencies are inferred from the claim text.