Fpga implementation of a real-time parallel mri reconstruction

Abstract

A system for parameterized FPGA (Field Programable Gate Array) implementation of real-time SENSE (SENSitivity Encoding) reconstruction including: a sensitivity maps memory configured to store sensitivity map data; an aliased image memory configured to store aliased image data acquired from a scanner; a reconstructed image memory configured to store reconstructed image data; a parameterized complex matrix multiplier; a pseudo-inverse calculator; a magnitude image block; and a controller; wherein sensitivity map data from the sensitivity maps memory is transferred to the pseudo-inverse calculator; wherein data from the pseudo-inverse calculator and the aliased image data from the aliased image memory is transferred to the complex matrix multiplier; wherein data from the complex matrix multiplier is transferred to the magnitude image block; wherein the controller is configured to generate an address of the sensitivity map memory and an address of the aliased image memory to access the encoding matrix and corresponding aliased image data and also configured to generate an address of the reconstructed image memory to store the reconstructed image data.

Dependencies are inferred from the claim text.