Circuit arrangement for clock synchronization
AssigneeIntel IP Corporation
InventorsSteffen Reinhardt, Peter Bode
Life of this patent
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Abstract
A circuit arrangement may include an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized signal having an ADC frequency, a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency. The sampling frequency is smaller than the ADC frequency. The circuit arrangement may further include a timer circuit providing a second signal having a timer frequency and a timing control signal to control the timing of the decimation circuit, and a difference determination circuit configured to determine a phase difference between the second signal and the first signal.
Claims20
A circuit arrangement, comprising:
- an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized radio signal having an ADC frequency;
- a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency, wherein the sampling frequency is smaller than the ADC frequency;
- a timer circuit providing a second signal having a timer frequency and a timing control signal to control the timing of the decimation circuit;
- and
- a difference determination circuit configured to determine a phase difference between the second signal and the first signal.
A circuit arrangement adapted for clock synchronization and signal conversion used in a mobile radio communication device, the circuit arrangement comprising:
- an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized radio signal having an ADC frequency;
- a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency, wherein the sampling frequency is smaller than the ADC frequency;
- a timer circuit providing a second signal having a timer frequency and a timing control signal to control the timing of the decimation circuit;
- a difference determination circuit configured to determine a frequency difference between the timer frequency and the sampling frequency.
A mobile radio communication device, comprising:
- a radio frequency circuit;
- and
- a circuit arrangement, comprising:
- an analog-to-digital-converter (ADC) configured to convert an analog signal into a digitized radio signal having an ADC frequency;
- a decimation circuit configured to provide a first signal having a sampling frequency based on the digitized radio signal having the ADC frequency, wherein the sampling frequency is smaller than the ADC frequency;
- a timer circuit providing a second signal having a timer frequency and a timing control signal to control the timing of the decimation circuit;
- and
- a difference determination circuit configured to determine a phase difference between the second signal and the first signal.
Dependencies are inferred from the claim text.