Parallel processing device and memory cache control method

A parallel processing device having a plurality of nodes, wherein the device comprises:

• a first node having:
• a first memory;
• and
• a processor coupled to the first memory and configured to execute a first process, the first process comprising;
• storing first data in the first memory;
• transmitting the first data to other nodes;
• and
• switching an use of the first data from a client cache to a server cache;
• a second node having:
• a second memory, and
• a second processor coupled to the second memory and configured to execute a second process, the second process comprising;
• storing the first data in the second memory that is slower than the first memory;
• recording data management information which indicates that the first data is being stored by the first node in the first memory;
• receiving a transmission request of the first, data from a third node;
• and
• referring to the data management information, when the transmission request is received, and instructing the first node to transmit the first data to the third node, if the use of the first data is switched to the server cache, and if the first data is stored in the first memory of the first node.