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US 2017/0366468 A1Published application
Low latency re-timer
AssigneeIntel Corporation
InventorsEhud SHOOR, Ari SHARON
Life of this patent
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Abstract
Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.
Claims19
An apparatus comprising:
- a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum;
- a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum;
- and
- a comparator to compare the first timestamp with the second timestamp.
1 more element
A system comprising:
- a memory;
- a processor coupled to the memory, wherein the processor is coupled to a first re-timer via an AC coupling capacitor, wherein the first re-timer comprises:
- a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide an RX spread spectrum clock (RX SSC) timestamp;
- a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a TX spread spectrum clock (TX SSC) timestamp;
- and
- a comparator to compare the RX SSC timestamp with the TX SSC timestamp;
- and
- a wireless interface to allow the processor to communicate with another device.
5 more elements
An apparatus comprising:
- a receiver logic to receive data from a first device;
- a transmitter logic to send data to a second device;
- a FIFO coupled to the receiver logic and to the transmitter logic, wherein data from the receiver is to enter the FIFO via a receive clock (RX Clk), and wherein the data from the FIFO is read out by a transmit clock (TX Clk) and is to be sent to the transmitter logic;
- and
- circuitry to substantially align a phase of the RX Clk with a phase of the TX Clk.
2 more elements
Dependencies are inferred from the claim text.