Digital Oversampling Clock And Data Recovery Circuit

At least one non-transitory computer readable storage medium comprising instructions that when executed enable a system to:

• oversample a first duration of incoming data in a first time-to-data converter (TDC) and hold the oversampled first duration during receipt of a second duration of the incoming data;
• oversample the second duration of the incoming data in a second TDC and hold the oversampled second duration during receipt of a third duration of the incoming data, wherein the first and second TDCs are to operate in opposing phases;
• filter the oversampled first duration and the oversampled second duration in a first filter coupled to the first and second TDCs and generate a control output therefrom;
• and
• generate a recovery clock signal in a digitally controller oscillator (DCO) signal based at least in part on the control output.

An apparatus comprising:

• a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data;
• a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data, the first and second TDCs to operate in opposing phases;
• a processing circuit coupled to the first TDC and the second TDC, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom, and a second filter to filter an output of the first filter;
• and
• a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.