US 2017/0366191 A1 · MULTIPLYING DELAY-LOCKED LOOP USING SAMPLING TIME-TO-DIGITAL CONVERTER

Abstract

A multiplying delay-locked loop circuit includes a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output, and a feedback loop including circuitry for deriving a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits. The circuitry for deriving a digital control signal includes a sampling time-to-digital converter (STDC) configured to operate on a time delay between inputs to generate the digital control signal. The STDC subtracts a second difference the signals derived from the delay chain output and output of the feedback divider from a first difference between the signals derived from the delay chain output and output of the feedback divider to provide a difference value, and the difference value indicates sign and magnitude of output offset in the delay chain output.

Claims20

Dependent claims

A multiplying delay-locked loop circuit, comprising:

a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output;
and
a feedback loop including circuitry for deriving, from feedback signals supplied by the delay chain, a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits in the plurality of variable delay circuits.

A method of controlling a multiplying delay-locked loop circuit, the multiplying delay-locked loop circuit including a delay chain and having a delay chain output, and a feedback loop including a feedback divider for dividing the delay chain output, the method comprising:

inputting, to a sampling time-to-digital converter, signals derived from (a) an output of a delay chain having a plurality of variable delay circuits that are connected in series and fed back in a feedback loop to input of the delay chain, and (b) an output of a feedback divider in the feedback loop, the feedback divider being configured to divide the delay chain output thereby multiplying output of the delay-locked loop circuit;
and
inputting an output signal of the sampling time-to-digital converter as a control signal to ones of the variable delay circuits in the plurality of variable delay circuits.

Dependencies are inferred from the claim text.

Multiplying delay-locked loop using sampling time-to-digital converter

Life of this patent

Multiplying delay-locked loop using sampling time-to-digital converter

Life of this patent

Abstract

Claims20