Phase-locked loops with electrical overstress protection circuitry

A method for operating a phase-locked loop on an integrated circuit, comprising:

• with a phase frequency detector within the phase-locked loop, receiving a reference clock signal;
• with a variable oscillator within the phase-locked loop, outputting a feedback clock signal to the phase frequency detector;
• and
• with a control block within the phase-locked loop, receiving the reference clock signal and the feedback clock signal and selectively deactivating the phase frequency detector in response to detecting that either the reference clock signal has stopped toggling or the feedback clock signal has stopped toggling.

Phase-locked loop circuitry, comprising:

• a phase frequency detector;
• a variable oscillator coupled to the phase frequency detector in a loop;
• a source follower transistor interposed in the loop;
• and
• a control block that selectively applies a predetermined voltage level to the source follower transistor in response to detecting a clock loss event.