Multiplexer-Memory Cell Circuit, Layout Thereof and Method of Manufacturing Same

An integrated circuit disposed in and on a substrate, the integrated circuit comprising:

• a field programmable gate array including:
• a first plurality of memory cells to store data, wherein each memory cell includes (i) a first output and (ii) at least one programming transistor;
• a second plurality of memory cells to store data, wherein each memory cell includes (i) a first output and (ii) at least one programming transistor, wherein the second plurality of memory cells is located adjacent to the first plurality of memory cells;
• a first multiplexer including a plurality of inputs, an output and a plurality of input selects;
• a first plurality of poly-silicon conductors, each poly-silicon conductor of the first plurality is disposed in the substrate and connected to the first output of an associated memory cell of the first plurality of memory cells;
• a first plurality of poly-silicon extensions, each poly-silicon extension having a first end and a second end, wherein each poly-silicon extension of the first plurality is (i) connected at a first end to an associated poly-silicon conductor of the first plurality of poly-silicon conductors and (ii) coupled at a second end to an associated input select of the first multiplexer, wherein the first plurality of poly-silicon extensions are disposed in the substrate and at least partially under a first metal conductor, which is disposed above the substrate, in the field programmable gate array;
• a second multiplexer including a plurality of inputs, an output and a plurality of input selects;
• and
• a second plurality of poly-silicon extensions, each poly-silicon extension of the second plurality having a first end and a second end, wherein each poly-silicon extension of the second plurality is (i) coupled at a first end to a second end of a unique poly-silicon extension of the first plurality of poly-silicon extensions and (ii) coupled at a second end to an associated input select of the second multiplexer, wherein the second plurality of poly-silicon extensions are disposed in the substrate and at least partially under a second metal conductor, which is disposed above the substrate, in the field programmable gate array.

An integrated circuit disposed in and on a substrate, the integrated circuit comprising:

• a field programmable gate array including:
• a first plurality of static memory cells to store data, wherein each memory cell includes a first output;
• a second plurality of static memory cells to store data, wherein each memory cell includes a first output;
• a first multiplexer including a plurality of inputs, an output and a plurality of input selects;
• a second multiplexer including a plurality of inputs, an output and a plurality of input selects;
• a first plurality of poly-silicon conductors, each poly-silicon conductor of the first plurality (i) includes first and second ends and is disposed in the substrate and (ii) is connected to the first output of an associated memory cell of the first plurality of static memory cells at the first end;
• a second plurality of poly-silicon conductors, each poly-silicon conductor of the second plurality (i) includes first and second ends and is disposed in the substrate and (ii) is connected to the first output of an associated memory cell of the second plurality of static memory cells at the first end;
• a first plurality of poly-silicon extensions, each poly-silicon extension of the first plurality is (i) connected to an associated poly-silicon conductor of the first plurality of poly-silicon conductors at the second end and (ii) coupled to an associated input select of the first multiplexer, wherein the first plurality of poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor, which is disposed above the substrate, in the field programmable gate array;
• a second plurality of poly-silicon extensions, each poly-silicon extension of the second plurality is (i) connected to an associated poly-silicon conductor of the second plurality of poly-silicon conductors at the second end and (ii) coupled to an associated input select of the second multiplexer, wherein the second plurality of poly-silicon extensions are disposed in the substrate and at least partially under a metal conductor, which is disposed above the substrate, in the field programmable gate array.