Integrated circuit (ic) chip comprising an identification circuit

An integrated circuit (IC) chip (300) with an identification number (ID), the IC chip including a scan chain (310) having a plurality of stages (301) connected in a chain, at least one of the plurality of stages comprising:

• an identification cell (110) configured to generate an ID bit that is a result of fabrication process of said IC chip;
• and
• a scan flip-flop (312) configured to selectively receive a scan data on a scan line (322) or the ID bit from the identification cell,
• wherein the identification cell comprises:
• a latch having a first output and a second output that are opposite to each other;
• and
• a first buffer and a second buffer provided on both sides of the latch and connected to the first output and the second output of the latch, respectively;
• wherein the latch includes two permanently mismatched CMOS inverters (122 and 124) that are cross-coupled with each other by directly connecting an input node (A1) of one of said two CMOS inverters (122) to an output node (B2) of another one of said two CMOS inverters (124), and by directly connecting an output node (B1) of said one of said two CMOS inverters (122) to an input node (A2) of said another one of said two CMOS inverters (124), and
• wherein the output of said one of said two CMOS inverters (122) functions as the first output of the latch, and the output of said another one of said two CMOS inverters (124) functions as the second output of the latch.