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US 2017/0366184 A1Published application
Apparatus and method for standby current control of signal path
AssigneeMicron Technology, Inc.
InventorTETSUYA ARAI
Life of this patent
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Abstract
Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.
Claims20
An apparatus comprising:
- an input terminal;
- an output terminal;
- and
- a plurality of logic circuits coupled in series between the input terminal and the output terminal, the plurality of logic circuits including a first logic circuit and a second logic circuit;
- wherein each of output nodes of the first logic circuit and the second logic circuit is configured to be precharged in a standby state;
- wherein the output node of the first logic circuit is further configured to be released from being precharged in a first reset operation following the standby state;
- and
- wherein the output node of the second logic circuit is further configured to be still precharged in the first reset operation.
5 more elements
An apparatus comprising:
- an input terminal;
- an output terminal;
- and
- a plurality of logic circuits coupled in series between the input terminal and the output terminal such that an output node of a proceeding one of the plurality of logic circuits is coupled to an input node of a succeeding one of the plurality of logic circuits, an input node of a first one of the plurality of logic circuits is coupled to the input terminal and an output node of a last one of the plurality of logic circuits is coupled to the output terminal;
- wherein each of output nodes of the plurality of logic circuits are configured to be precharged in a standby state;
- wherein each of odd numbered one or ones of output nodes of the plurality of logic circuits is configured to be released from being precharged in a first reset operation following the standby state;
- and
- wherein each of even numbered one or ones of output nodes of the plurality of logic circuits is configured to be still precharged in the first reset operation.
5 more elements
A method comprising:
- precharging, in a standby state, each of output nodes of the plurality of logic circuits, the plurality of logic circuits coupled in series such that an output node of a proceeding one of the plurality of logic circuits is coupled to an input node of a succeeding one of the plurality of logic circuits;
- stopping precharging, in a first reset operation following the standby state, each of odd numbered one or ones of the output nodes of the plurality of logic circuits;
- and
- keeping precharging, in the first reset operation, each of even numbered one or ones of the output nodes of the plurality of logic circuits.
1 more element
Dependencies are inferred from the claim text.