Semiconductor memory device for calibrating a termination resistance and a method of calibrating the termination resistance thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsHANGI JUNG, HUN-DAE CHOI, JINHYEOK BAEK
Life of this patent
Estimating the term…
Abstract
A memory device includes a first on-die termination circuit, a second on-die termination circuit, a voltage generator, and a code generator. The first on-die termination circuit may correspond to a data input buffer. The second on-die termination circuit may correspond to a command/address buffer. The voltage generator may generate a reference voltage. The code generator may generate a resistance calibration code of a selected one of the on-die termination circuits in response to the reference voltage. The reference calibration code may calibrate a resistance value of the selected on-die termination circuit.
Claims21
A memory device comprising:
- a first on-die termination circuit corresponding to a data input buffer;
- a second on-die termination circuit corresponding to a command/address buffer;
- a voltage generator configured to generate a reference voltage;
- and
- a code generator configured to generate a resistance calibration code of a selected one of the first and second on-die termination circuits in response to the reference voltage,
- wherein the resistance calibration code calibrates a resistance value of the selected on-die termination circuit.
A method of generating a resistance calibration code of a memory device for calibrating resistance values of first and second on-die termination circuits, the method comprising:
- generating, at a code generator, a first resistance calibration code for the first on-die termination circuit;
- changing, at the code generator and a voltage generator, a first generation condition of the resistance calibration code to a second generation condition of the resistance calibration code for the second on-die termination circuit;
- and
- generating, at the code generator, a second resistance calibration code for the second on-die termination circuit using the second generation condition.
(canceled)
A termination resistance calibration circuit of a memory device, comprising:
- a first on-die termination circuit configured to operate in response to a first resistance calibration code;
- a second on-die termination circuit configured to operate in response to a second resistance calibration code;
- a control circuit configured to generate an update signal, a first calibration signal, and a second calibration signal in response to a calibration clock signal and a calibration start signal;
- a voltage generator configured to generate a reference voltage in response to the first calibration signal and the second calibration signal;
- a code generator configured to generate a resistance calibration code in response to the reference voltage;
- and
- a code register configured to generate the first resistance calibration code and the second resistance calibration code in response to the resistance calibration code, the first calibration signal, the second calibration signal, and the update signal,
- wherein the code generator comprises:
- a first pull-up set connected to a first node;
- a second pull-up set connected to a second node and the first pull-up set;
- a pull-down set connected between the second node and ground;
- a first comparator configured to compare a first voltage of the first node and the reference voltage;
- and.
- a second comparator configured to compare a second voltage of the second node and the reference voltage.
Dependencies are inferred from the claim text.