High-frequency delay-locked loop and clock processing method for same

A high-frequency delay-locked loop, characterized by comprising:

• a DLL circuit and a DCC circuit which are sequentially connected in series, and
• a pulse generating circuit used for generating a clock having a fixed pulse width, the fixed pulse width being a high level width of the clock having the fixed pulse width and not smaller than a minimum pulse width required by the DLL circuit,
• wherein the clock having the fixed pulse width is input into the DLL circuit.

A clock processing method for a high-frequency delay-locked loop, wherein the high-frequency delay-locked loop comprises a DLL circuit and a DCC circuit that are sequentially connected in series, characterized in that the clock processing method comprises using a pulse generating circuit to generate a clock having a fixed pulse width, wherein the fixed pulse width is a high level width of the clock having the fixed pulse width and not smaller than the minimum pulse width required by the DLL circuit, wherein the clock having the fixed pulse width is input into the input of the DLL circuit, and wherein the pulse generating circuit generating the clock having the fixed pulse width comprises generating a delayed input clock after the input clock is delayed by a fixed delay, with the rising edge of the input clock generating the rising edge of the clock having the fixed pulse width and the rising edge of the delayed input clock generating the falling edge of the clock having the fixed pulse width.

A high-frequency delay-locked loop, characterized by comprising:

• a DLL circuit and a DCC circuit which are sequentially connected in series, and
• a pulse generating circuit used for generating a clock having a fixed pulse width, the fixed pulse width being a high level width of the clock having the fixed pulse width and not smaller than a minimum pulse width required by the DLL circuit, and the fixed pulse width enabling a low level width of the clock having the fixed pulse width to be not smaller than the minimum pulse width required by the DLL circuit,
• wherein the clock having the fixed pulse width is input into the DLL circuit.

A clock processing method for a high-frequency delay-locked loop, wherein the high-frequency delay-locked loop comprises a DLL circuit and a DCC circuit that are sequentially connected in series,

• characterized in that the clock processing method comprises using a pulse generating circuit to generate a clock having a fixed pulse width, wherein the fixed pulse width is a high level width of the clock having the fixed pulse width and not smaller than the minimum pulse width required by the DLL circuit, wherein the fixed pulse width enables a low level width of the clock having the fixed pulse width to be not smaller than a minimum pulse width required by the DLL circuit, wherein the clock having the fixed pulse width is input into the input of the DLL circuit, and wherein the pulse generating circuit generating the clock having the fixed pulse width comprises generating a delayed input clock after the input clock is delayed by a fixed delay, with the rising edge of the input clock generating the rising edge of the clock having the fixed pulse width and the rising edge of the delayed input clock generating the falling edge of the clock having the fixed pulse width.