Integrated circuit and method of testing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJinn-Yeh CHIEN
Life of this patent
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Abstract
An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback path. The circuit is configured to receive a first voltage signal that is either a substantially low logic level signal or a substantially high logic level signal. The circuit is configured to generate an oscillating signal from the first voltage signal, and the counter is configured to count oscillations of the oscillating signal.
Claims20
A method of testing a circuit, the method comprising:
- electrically connecting a test circuit to the circuit;
- selecting a loopback path from a plurality of loopback paths in the circuit, wherein a data path of the circuit is electrically coupled to the selected loopback path;
- receiving a first voltage signal, wherein the first voltage signal is a substantially low logical level signal or a substantially high logical level signal;
- generating a second voltage signal from the first voltage signal, wherein the first voltage signal is applied to the data path, and wherein the second voltage signal oscillates between the substantially low logical level and the substantially high logical level at an oscillation frequency;
- and
- measuring the oscillation frequency of the second voltage signal.
An integrated circuit for testing a circuit, the integrated circuit comprising:
- a first circuit comprising a loopback path electrically coupled to an inverter;
- and
- a test circuit comprising a controller and a counter, wherein the test circuit is electrically coupled to the first circuit, and wherein the controller is configured to select the loopback path, wherein
- the first circuit is configured to:
- receive a first voltage signal, wherein the first voltage signal is either a substantially low logic level signal or a substantially high logic level signal, and
- generate an oscillating signal from the received first voltage signal, and the counter is configured to count oscillations of the oscillating signal.
A test circuit, comprising:
- a controller electrically coupled to a first circuit, and configured to activate a first feedback path of the first circuit, disable a second feedback path of the first circuit, and output a first voltage signal, wherein the first voltage signal is either a substantially low logic level signal or a substantially high logic level signal;
- a frequency counter electrically coupled to the controller and configured to receive a second voltage signal from the first circuit, wherein the second voltage signal is derived from the first voltage signal;
- an interface electrically coupled to the controller and the frequency counter, wherein the interface is configured to receive a counter output signal from the frequency counter;
- and
- an output pad electrically coupled to an output terminal of the interface, and configured to receive a measured oscillation frequency of the first circuit.
Dependencies are inferred from the claim text.