Reduced power set-reset latch based flip-flop

A method comprising:

• coupling a first circuit and a second circuit of a master latch circuit to a first shared circuit node;
• coupling a third circuit and a fourth circuit of a slave latch circuit to a second shared circuit node;
• storing, by the master latch circuit, a value of an input signal in response to an assertion of a clock signal;
• storing, by the slave latch circuit, an output value of the master latch circuit in response to a de-assertion of the clock signal;
• and
• de-coupling, by the master latch circuit, the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.

A system, comprising:

• a clock source configured to generate a clock signal;
• a circuit block configured to generate a data signal;
• and
• a flip-flop circuit including a master latch circuit and a slave latch circuit, wherein the master latch circuit includes a first circuit and a second circuit coupled to a first shared circuit node, wherein the slave latch circuit includes a third circuit and a fourth circuit coupled to a second shared circuit node, and wherein the flip-flop circuit is configured to:
• store a value of an input signal in the master latch circuit in response to an assertion of a clock signal;
• store an output value of the master latch circuit in the slave latch circuit in response to a de-assertion of the clock signal;
• and
• de-couple the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.