Compact chireix combiner and impedance matching circuit

A Chireix combiner circuit being configured to combine RF power from first and second amplified RF signals that are equal in magnitude and opposite in phase, the Chireix combiner circuit comprising:

• first and second input ports;
• a summing node;
• a first branch connected between the first input port and the summing node, the first branch comprising a first LC network and a first impedance matching network, the first impedance matching network being configured to match an input impedance of the first branch to a fixed value, the first impedance matching network and the first LC network being collectively configured to phase shift the first amplified RF signal for an outphasing operation using common reactive components for the match of the input impedance of the first branch and the outphasing operation;
• and
• a second branch connected between the second input port and the summing node, the second branch comprising a second LC network and a second impedance matching network, the second impedance matching network being configured to match an input impedance of the second branch to a fixed value, the second impedance matching network and the second LC network being collectively configured to phase shift the second amplified RF signal for an outphasing operation using common reactive components for the match of the input impedance the second branch and the outphasing operation.

A method of amplifying an RF signal, comprising:

• separating and amplifying the RF signal using first and second amplifiers into first and second amplified RF signals, the second amplified RF signal having the same frequency and being phase shifted from the first amplified RF signal;
• feeding the first and second amplified RF signals into a combiner circuit, the combiner circuit comprising a first branch connected between a first output terminal of the first amplifier and a summing node and a second branch connected between a second output terminal of the second amplifier and the summing node, the first branch comprising a first LC network and a first output matching network being configured to match an input impedance of the first branch to an optimal load impedance of the first amplifier, the second branch comprising a second LC network and a second output matching network being configured to match an input impedance of the second branch to an optimal load impedance of the second amplifier;
• and
• combining RF power from the first and second amplified RF signals into the summing node using the combiner circuit, wherein combining the RF power comprises phase shifting the first amplified RF signal for an outphasing operation between the first output node and the summing node using the first LC network and the first output matching network and phase shifting the second amplified RF signal for an outphasing operation between the second output node and the summing node using the second LC network and the second output matching network,
• wherein the phase shifting of the first amplified RF signal for an outphasing operation between the first output node and the summing node is performed using common reactive components from the first output matching network, and
• wherein the phase shifting of the second amplified RF signal for an outphasing operation between the second output node and the summing node is performed using common reactive components from the second output matching network.