Apparatus and methods for actively-controlled trigger and latch release thyristor

A method for protecting an integrated circuit from electrical overstress, the method comprising:

• controlling a voltage of a dummy supply node based on a voltage of a signal node using an overvoltage sense circuit;
• detecting a presence of a transient overstress event at the signal node based on the voltage of the dummy supply node using an active trigger and latch release circuit;
• activating one or more trigger signals in response to detecting the presence of the transient overstress event using the active trigger and latch release circuit;
• and
• controlling an activation voltage of a silicon controlled rectifier (SCR) that is electrically connected between the signal node and a discharge node based on the one or more trigger signals.

A packaged system comprising:

• a lead;
• a first system on a chip (SOC) electrically connected to the lead, wherein the first SOC comprises:
• a silicon controlled rectifier (SCR) electrically connected between a signal node and a discharge node, wherein the SCR is configured to receive one or more trigger signals that are operable to control an activation voltage of the SCR;
• an overvoltage sense circuit configured to control a voltage of a dummy supply node based on a voltage of the signal node;
• and
• an active trigger and latch release circuit configured to detect presence of a transient overstress event at the signal node based on a voltage difference between the dummy supply node and the discharge node, wherein the active trigger and latch release circuit is further configured to activate the one or more trigger signals in response to detecting presence of the transient overstress event.