Transient Voltage Protection Circuits, Devices, and Methods

An electrostatic discharge (ESD) protection circuit comprising:

• a power MOSFET for discharging an electrostatic discharge current coupled between an input pad and an output of the ESD protection circuit;
• a trigger circuit for triggering the power MOSFET, the trigger circuit coupled to a gate node of the power MOSFET, the trigger circuit comprising:
• a first trigger element string for controlling a gate to source voltage of the power MOSFET, wherein each trigger element of the first trigger element string comprises a bipolar transistor, a substrate diode, and a voltage divider to divide a voltage across adjacent trigger elements of the first trigger element string;
• and
• a second trigger element string for triggering the gate of the power MOSFET.

An electrostatic discharge (ESD) protection device comprising:

• a first trigger transistor disposed above a semiconductor substrate having a first doping type, the first trigger transistor comprising:
• a first buried region of a second doping type disposed over the semiconductor substrate, a first well region of the first doping type, a first doped region of the first doping type disposed in the first well region, a second doped region of the second doping type disposed in the first well region, and a third doped region of the second doping type disposed over the first buried region, wherein the second doping type is opposite to the first doping type, and wherein the second doped region and the first well region form a first Zener diode;
• a first substrate diode at an interface between the semiconductor substrate and the first well region;
• and
• a first resistive layer disposed in or over the semiconductor substrate, the first resistive layer coupled between the first doped region and the second doped region.

An electrostatic discharge protection system comprising:

• a circuit board comprising a first pad and a second pad;
• a device under protection bonded to the circuit board coupled between the first pad and the second pad;
• a power MOSFET bonded to the circuit board coupled between the first pad and the second pad, the power MOSFET comprising a control node, wherein the power MOSFET is configured to discharge a voltage that is negative relative to a ground voltage;
• a plurality of Zener NPN transistors bonded to the circuit board and coupled in series between the first pad and the control node of the power MOSFET;
• and
• a plurality of resistors coupled between each of the plurality of Zener NPN transistors, wherein the plurality of resistors are configured to divide a voltage across adjacent ones of the plurality of Zener NPN transistors.