Vertical transistor having uniform bottom spacers
AssigneeInternational Business Machines Corporation
InventorsKANGGUO CHENG, JUNTAO LI, GENG WANG, QINTAO ZHANG
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Abstract
A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.
Claims20
A method of forming a spacer for a vertical transistor, the method comprising:
- forming a fin on a semiconductor substrate;
- forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin;
- and
- epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin.
A method of forming a uniform spacer for vertical transistors, the method comprising:
- forming fins on a semiconductor substrate with sacrificial spacers on respective sidewalls thereof;
- forming source/drain (S/D) junctions at an upper surface of the semiconductor substrate and at respective bases of the fins;
- epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the S/D junctions between and at opposite sides of each of the fins;
- and
- replacing at least respective portions of the sacrificial spacer of each of the fins with components of the vertical transistors.
A vertical transistor structure, comprising:
- fins extending upwardly from doped regions of a semiconductor substrate;
- vertical transistor structures disposed on the fins;
- and
- an epitaxially grown rare earth oxide (REO) spacer with a substantially uniform thickness which is disposed between respective upper surfaces of the first and second doped regions and respective lower surfaces of the vertical transistor structures and between and at opposite sides of the fins.
Dependencies are inferred from the claim text.