Integration of strained silicon germanium pfet device and silicon nfet device for finfet structures

A method of forming a finFET transistor device, the method comprising:

• thinning a silicon-on-insulator (SOT) layer formed over a buried oxide (BOX) layer;
• epitaxially growing a crystalline, compressive strained silicon germanium (cSiGe) layer on the thinned SOT layer;
• performing a thermal process so as to drive germanium from the cSiGe layer into the thinned SOT layer;
• masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer;
• subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer;
• performing an annealing process so as to recrystallize the rSiGe layer;
• recessing the recrystallized rSiGe layer;
• epitaxially growing a tensile strained silicon layer on the rSiGe layer;
• and
• patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

A method of forming a semiconductor device, the method comprising:

• transforming a crystalline, compressive strained silicon germanium material to a relaxed SiGe material;
• recrystallizing the relaxed SiGe;
• and
• epitaxially growing a tensile strained silicon material on the relaxed SiGe material.