US 2017/0365683 A1 · POWER DEVICE HAVING A POLYSILICON-FILLED TRENCH WITH A TAPERED OXIDE THICKNESS

Abstract

In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

Claims20

Dependent claims

A semiconductor device comprising:

a silicon-containing semiconductor material having a top surface;
a first trench etched into the top surface to a first depth, the first trench having sidewalls;
a tapered silicon dioxide layer formed over the sidewalls, the tapered silicon dioxide layer being thermally grown over the sidewalls so as to convert a portion of the silicon-containing semiconductor material to the tapered silicon dioxide layer,
the tapering of the silicon dioxide layer being formed without etching the silicon dioxide layer;
a conductive material at least partially filling the first trench;
a first electrode overlying the silicon-containing semiconductor material;
and
a second electrode, wherein current is conducted between the first electrode and second electrode when the device is turned on.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/676,792Filed 14 Aug 2017

Priority

8 Sep 2015

Published

21 Dec 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10D 12/031
Manufacture or treatment: of igbts
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 62/107
Having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or…:…

Family

Application62/215,563Us provisional application · filed 8 Sep 2015

Application62/218,375Us provisional application · filed 14 Sep 2015

Application15/247,510Continuation · filed 25 Aug 2016

Application15/676,792Continuation

US 10,510,863 B2Related patent

US 2017/0069727 A1Published application

US 9,812,548 B2Related patent

US 2017/0365683 A1This patent

From the US filing history. Foreign family members aren’t listed.

Power device having a polysilicon-filled trench with a tapered oxide thickness

Life of this patent

Power device having a polysilicon-filled trench with a tapered oxide thickness

Life of this patent

Abstract

Claims20