Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices

A semiconductor device comprising:

• a substrate having a first region and a second region;
• a first plurality of Fin Field Effect Transistors (FinFETs) are present in a first region of the substrate, the first plurality of Fin Field Effect Transistors including a first set of fin structures having a first pitch, and merged epitaxial semiconductor material of a single composition on source and drain region portions of the first set of fin structures;
• and
• a second plurality of Fin Field Effect Transistors (FinFETs) is present in the second region of the substrate, the second plurality of FinFETs include a second set of fin structures having a second pitch that is at least 1.5× greater than the first pitch of the first set of fin structures, wherein the second plurality of FinFETs include a composite epitaxial semiconductor material on the source and drain region portions of the second set of fin structures, the composite epitaxial semiconductor material includes a first non-merged portion, and a second bridging portion extending into contact between adjacent fin structures in the second set of fin structures.

A semiconductor device comprising:

• a substrate having a first region and a second region;
• a first plurality of Fin Field Effect Transistors (FinFETs) are present in a first region of the substrate, the first plurality of Fin Field Effect Transistors including a first set of fin structures having a first pitch, and merged epitaxial semiconductor material of a single composition on source and drain region portions of the first set of fin structures, wherein the first plurality of the Field Effect Transistors (FinFETs) have a first applied voltage of 1.2 V or less;
• and
• a second plurality of Fin Field Effect Transistors (FinFETs) is present in the second region of the substrate, the second plurality of FinFETs include a second set of fin structures having a second pitch that is at least 1.5× greater than the first pitch of the first set of fin structures, wherein the second plurality of FinFETs include a composite epitaxial semiconductor material on the source and drain region portions of the second set of fin structures, the composite epitaxial semiconductor material includes a first non-merged portion, and a second bridging portion extending into contact between adjacent fin structures in the second set of fin structures, wherein the second plurality of the Field Effect Transistors (FinFETs) have a second applied voltage of more than 1.2V.