Gate patterning for ac and dc performance boost

A method, comprising:

• forming a multilayer stack for a gate on a substrate, said multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon;
• patterning a hard mask layer formed above said gate electrode layer to define a patterned hard mask, said patterned hard mask having a plurality of elements;
• forming a cut mask above said patterned hard mask layer, said cut mask having an opening exposing first portions of said patterned hard mask;
• etching said patterned hard mask through said opening to define a plurality of pairs of axially aligned hard mask segments above said first portions of said partially etched gate electrode layer;
• etching partially into said gate electrode layer through said patterned hard mask to define multiple partially etched gate stacks and a partially etched gate electrode layer, each of said multiple partially etched gate stacks including a pair of axially aligned gate stack segments;
• forming a conformal protective layer over at least lateral surfaces of said partially etched gate electrode layer and said patterned hard mask;
• and
• etching through a remainder of said partially etched gate electrode layer in the presence of said conformal protective layer to define a plurality of pairs of axially aligned gate structures from said axially aligned gate stack segments.