US 2017/0365672 A1 · COMPOSITE GATE DIELECTRIC LAYER APPLIED TO GROUP III-V SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

Abstract

The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlxY2-xO3 interface passivation layer formed onthe group III-V substrate; and a high dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2≦x≦1.9.The composite gate dielectric layer modifies the AI/Y ratio of the AlxY2-xO3 interface passivation layer, changes the average number of atomic coordination in the AlxY2-xO3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlxY2-xO3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improvestolerance of the dielectric layer on the voltage, and improvesthe quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.

Claims13

Dependent claims

A composite gate dielectric layer for a Group III-V substrate, comprising:

an AlxY2-xO3 interface passivation layer formed on the group III-V substrate;
and
a high dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2≦x≦1.9.

A method for manufacturing a composite gate dielectric layer for a group III-V substrate, comprising the following steps of:

Step 1:
cleaning the group III-V substrate, growing an Al2Om passivation layer on the group III-V substrate, wherein 2.5≦m≦3;
Step 2:
growing a Y2O. strengthening layer on the Al2Om passivation layer, wherein 2.5≦n≦3;
Step 3:
thermally treating the Al2Om passivation layer and the Y2On strengthening layer in situ to mix the Al2Om passivation layer and the Y2On strengthening layer to obtain an interface passivation layer of AlxY2-xO3, wherein 1.2≦x≦1.9;
and
Step 4:
growing a high dielectric insulating layer on the AlxY2-xO3 interface passivation layer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/539,597Filed 16 Jul 2015

Published

21 Dec 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 64/118
Electrodes of devices having potential barriers: electrodes comprising insulating layers having particular dielectric or electrostatic properties,…
H10D 64/01358
Of electrodes having a conductor capacitively coupled to a semiconductor by an insulator: the insulator being formed after the semiconductor body,…
H10D 64/514
For igfets: characterised by the insulating layers
H10D 64/685
Having a compositional variation, e.g. multilayered: being perpendicular to the channel plane

Composite gate dielectric layer applied to group iii-v substrate and method for manufacturing the same

Life of this patent

Composite gate dielectric layer applied to group iii-v substrate and method for manufacturing the same

Life of this patent

Abstract

Claims13