Semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorsYasuyuki HOSHI, Masahito OTSUKI, Shoji YAMADA, Takashi SHIIGI
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AssigneeFuji Electric Co., Ltd.
InventorsYasuyuki HOSHI, Masahito OTSUKI, Shoji YAMADA, Takashi SHIIGI
Estimating the term…
On a front surface of an n+-type SiC substrate becoming a drain region, an n−-type drift layer, a p-type base layer, and an n+-type source layer are sequentially formed by epitaxial growth. In the n+-type source layer, the p+-type contact region is selectively provided. A trench is provided penetrating the n+-type source layer and the p-type base layer in the depth direction and reaching the n−-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 μm or less. A depth of the trench is, for example, 1 μm or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.
A semiconductor device comprising:
Dependencies are inferred from the claim text.