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US 2017/0365618 A1Published application
Systems including memory cells on opposing sides of a pillar
AssigneeMicron Technology, Inc.
InventorTheodore T. Pekny
Life of this patent
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Abstract
Systems including a processor and a memory device in communication with the processor include an array of non-volatile memory cells configured in a NAND architecture. The array includes a plurality of series-coupled first non-volatile memory cells, each first non-volatile memory cell curving around a first curved side of a substantially vertical pillar and terminating at an isolation region, and a plurality of series-coupled second non-volatile memory cells, each second non-volatile memory cell curving around a second curved side of the substantially vertical pillar and terminating at the isolation region. Respective ones of the first non-volatile memory cells are respectively at same vertical levels as respective ones of the second non-volatile memory cells.
Claims24
A system, comprising:
- a processor;
- and
- a memory device in communication with the processor, wherein the memory device comprises an array of non-volatile memory cells configured in a NAND architecture, the array of non-volatile memory cells comprising:
- a plurality of series-coupled first non-volatile memory cells, each first non-volatile memory cell of the plurality of series-coupled first non-volatile memory cells curving around a first curved side of a substantially vertical pillar and terminating at an isolation region;
- a plurality of series-coupled second non-volatile memory cells, each second non-volatile memory cell of the plurality of series-coupled second non-volatile memory cells curving around a second curved side of the substantially vertical pillar and terminating at the isolation region;
- wherein respective ones of the first non-volatile memory cells of the plurality of series-coupled first non-volatile memory cells are respectively at same vertical levels as respective ones of the second non-volatile memory cells of the plurality of series-coupled second non-volatile memory cells.
3 more elements
A system, comprising:
- a processor;
- and
- a memory device in communication with the processor, wherein the memory device comprises an array of non-volatile memory cells configured in a NAND architecture, the array of non-volatile memory cells comprising:
- a conductive pillar;
- a plurality of first non-volatile memory cells on a first side of the pillar coupled in series by the conductive pillar, each first non-volatile memory cell of the plurality of first non-volatile memory cells comprising a respective portion of a first charge trap adjacent to the first side of conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap;
- a plurality of second non-volatile memory cells on a second side of the pillar, opposite to the first side of the pillar, coupled in series by the conductive pillar, each second non-volatile memory cell of the plurality of second non-volatile memory cells comprising a respective portion of a second charge trap adjacent to the second side of the conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap;
- and
- a single select transistor that selectively couples the plurality of first non-volatile memory cells and the plurality of second non-volatile memory cells to one of a source line and a data line;
- wherein each first control gate of the plurality of first non-volatile memory cells is electrically isolated from each second control gate of the plurality of second non-volatile memory cells;
- and
- wherein respective ones of the first non-volatile memory cells of the plurality of first non-volatile memory cells are respectively at same vertical levels as respective ones of the second non-volatile memory cells of the plurality of second non-volatile memory cells.
8 more elements
A system, comprising:
- a processor;
- and
- a memory device in communication with the processor, wherein the memory device comprises an array of non-volatile memory cells configured in a NAND architecture, the array of non-volatile memory cells comprising:
- a first pair of electrically isolated activation lines formed on opposing sides of one or more conductive pillars;
- a second pair of electrically isolated activation lines formed on opposing sides of the one or more conductive pillars;
- and
- a plurality of charge storage nodes, wherein each charge storage node of the plurality of charge storage nodes is interposed between a respective conductive pillar of the one or more conductive pillars and a respective activation line of first pair of electrically isolated activation lines or the second pair of electrically isolated activation lines;
- wherein a non-volatile memory cell formed at an intersection of a first one of the first pair of activation lines and a given one of the conductive pillars, and a non-volatile memory cell formed at an intersection of a first one of the second pair of activation lines and the given one of the conductive pillars, form at least a portion of a first serially-coupled string of non-volatile memory cells;
- wherein a non-volatile memory cell formed at an intersection of a second one of the first pair of activation lines and the given one of the conductive pillars, and a non-volatile memory cell formed at an intersection of a second one of the second pair of activation lines and the given one of the conductive pillars, form at least a portion of a second serially-coupled string of non-volatile memory cells;
- and
- wherein the first one of the first pair of activation lines and the first one of the second pair of activation lines are formed on the same side of the given one of the conductive pillars.
8 more elements
Dependencies are inferred from the claim text.