Ldmos design for a finfet device

A method for manufacturing a semiconductor device, the method comprising:

• providing a semiconductor structure, the semiconductor structure comprising:
• a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type, the first and second regions being laterally adjacent to each other, the first conductivity type being different from the second conductivity type;
• a first fin and a second fin protruding from the semiconductor substrate and separated from each other by a trench, the first fin including first and second portions of the first conductivity type and disposed on the first region and a third portion of the second conductivity type disposed on the second region, the first portion having an upper surface lower than an upper surface of the second portion, the second and third portions being laterally adjacent to each other;
• the second fin being of the second conductivity type and disposed on the second region;
• and
• a first insulator layer filling at least a portion of the trench;
• forming a first gate structure surrounding a portion of the second portion and a portion of the third portion, the first gate structure comprising:
• a first distal end on the first portion and a second distal end on the first insulator layer;
• a gate insulator layer on a surface portion of the first portion, the second portion, and the third portion;
• a first gate on the gate insulator layer;
• and
• a hardmask layer surrounding the first gate;
• forming an interlayer dielectric layer on the first gate structure;
• planarizing the interlayer dielectric layer and the hardmask layer to expose the first gate;
• removing the first gate to expose the gate insulator layer and a surface portion of the first insulator layer;
• forming a first work function adjusting layer on a portion of the gate insulator layer on the surface portion of the first portion and on the second portion;
• and
• forming a second work function adjusting layer on the first work function adjusting layer, the gate insulator layer on the third portion, and the exposed surface portion of the first insulator layer.