Using Inter-Tier Vias in Integrated Circuits

A three-dimensional (3D) integrated circuit (IC), comprising:

• a plurality of tiers disposed on a substrate layer, wherein the plurality of tiers comprises:
• a first tier having a first active device layer electrically coupled to one or more first interconnect layers;
• a second tier having a second active device layer electrically coupled to a second interconnect layer, wherein the first tier is positioned closer to the substrate layer than the second tier, and wherein the one or more first interconnect layers include an uppermost first interconnect layer that is least proximate to the first active device layer of the first interconnect layers;
• one or more first inter-tier vias (IVs) configured to electrically couple the second interconnect layer and the uppermost first interconnect layer;
• wherein the uppermost first interconnect layer is electrically coupled to a power source at one or more peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer;
• wherein the uppermost first interconnect layer is electrically coupled to the power source at the one or more peripheral locations of the first tier using one or more peripheral input structures, wherein respective peripheral input structures comprise:
• a first through silicon via (TSV) electrically coupled to the uppermost first interconnect layer;
• and
• a first solder bump disposed at a top side of the second tier, electrically coupled to the TSV, and configured to receive power from the power source;
• and
• further comprising one or more central input structures positioned proximate to a center of the 3D IC and coupled to the power source, wherein the one or more central input structures comprise:
• a second through silicon via (TSV) electrically coupled to the uppermost first interconnect layer;
• and
• a second solder bump disposed at the top side of the second tier, electrically coupled to the TSV, and configured to receive power from the power source.

A three-dimensional (3D) integrated circuit (IC), comprising:

• a plurality of tiers disposed on a substrate layer, wherein the plurality of tiers comprises:
• a first tier having a first active device layer electrically coupled to one or more first interconnect layers;
• a second tier having a second active device layer electrically coupled to a second interconnect layer, wherein the first tier is positioned closer to the substrate layer than the second tier, and wherein the one or more first interconnect layers include an uppermost first interconnect layer that is least proximate to the first active device layer of the first interconnect layers;
• one or more first inter-tier vias (IVs) configured to electrically couple the second interconnect layer and the uppermost first interconnect layer;
• wherein the uppermost first interconnect layer is electrically coupled to a power source at one or more peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer;
• wherein the uppermost first interconnect layer is electrically coupled to the power source at the one or more peripheral locations of the first tier using one or more peripheral input structures, wherein respective peripheral input structures comprise:
• a through silicon via (TSV) electrically coupled to the uppermost first interconnect layer;
• and
• a solder bump disposed at a top side of the second tier, electrically coupled to the TSV, and configured to receive power from the power source;
• and
• wherein the uppermost first interconnect layer is electrically coupled to an adjacent first interconnect layer, wherein:
• the adjacent first interconnect layer is larger in pitch than the uppermost first interconnect layer;
• and
• the adjacent first interconnect layer is electrically coupled to the TSV, thereby electrically coupling the TSV to the uppermost first interconnect layer.

A three-dimensional (3D) integrated circuit (IC), comprising:

• a plurality of tiers disposed on a substrate layer, wherein the plurality of tiers comprises:
• a first tier having a first active device layer electrically coupled to one or more first interconnect layers;
• a second tier having a second active device layer electrically coupled to one or more second interconnect layers, wherein the first tier is positioned closer to the substrate layer than the second tier, and wherein the one or more first interconnect layers include an uppermost first interconnect layer that is least proximate to the first active device layer of the first interconnect layers;
• one or more first inter-tier vias (IVs) configured to couple to one of the one or more second interconnect layers and to the uppermost first interconnect layer;
• and
• wherein the uppermost first interconnect layer is electrically coupled to a clock source, an input signal source, or combinations thereof at one or more peripheral locations of the first tier, thereby electrically coupling the clock source, the input signal source, or combinations thereof to the first active device layer and to the second active device layer.

An integrated circuit, comprising:

• an active device layer disposed on a substrate layer;
• a first interconnect layer disposed on a top side of the active device layer and electrically coupled to the active device layer;
• one or more second interconnect layers disposed on a bottom side of the active device layer;
• one or more first inter-tier vias (IVs) configured to couple to the first interconnect layer and to one of the one or more second interconnect layers;
• and
• wherein the one or more second interconnect layers is electrically coupled to a power source, a clock source, an input signal source, or combinations thereof, thereby electrically coupling the power source, the clock source, the input signal source, or combinations thereof to the active device layer.