Semiconductor device and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSeungyoung LEE, Sanghoon BAEK, Jung-Ho DO
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.
Claims20
A method of fabricating a semiconductor device, the method comprising:
- preparing a layout pattern;
- manufacturing a photomask using the layout pattern;
- and
- forming metal lines and vias on a substrate, using the photomask, the vias electrically connecting the metal lines,
- wherein the preparing the layout pattern comprises:
- laying out a first via pattern, a first lower metal pattern, and a first upper metal pattern, the first via pattern being at a first intersect area between the first lower metal pattern and the first upper metal pattern;
- laying out a second via pattern, a second lower metal pattern, and a second upper metal pattern, the second via pattern being at a second intersect area between the second lower metal pattern and the second upper metal pattern;
- categorizing the first via pattern into a risk via;
- and
- swapping a first group of the first via pattern and the first upper metal pattern with a second group of the second via pattern and the second upper metal pattern.
A method of fabricating a semiconductor device, the method comprising:
- laying out a plurality of lower metal lines that extend in a first direction, and a plurality of lower vias electrically connected to a lower surface of the plurality of lower metal lines;
- laying out a plurality of upper metal lines that extend in a second direction crossing the first direction, and a plurality of upper vias electrically connecting the plurality of upper metal lines to the lower metal lines;
- identifying a risk via from among the plurality of upper vias;
- and
- swapping a first group of a first upper metal line connected to the identified risk via and the plurality of upper vias connected to the first upper metal line, with a second group of a second upper metal line that is not connected to the identified risk via and the plurality of upper vias connected to the second upper metal line.
A method of fabricating a semiconductor device, the method comprising:
- laying out first and second lower metal patterns extending in a first direction;
- laying out first and second upper metal patterns extending in a second direction crossing the first direction;
- laying out a first via pattern between the first lower metal pattern and the first upper metal pattern and a second via pattern between the second lower metal pattern and the second upper metal pattern;
- swapping a first group of the first via pattern and the first upper metal pattern with a second group of the second via pattern and the second upper metal pattern;
- forming first and second lower metal lines on a substrate using a first photomask manufactured based on the first and second lower metal patterns;
- forming first and second upper metal lines on the first and second lower metal lines using a second photomask manufactured based on the first and second upper metal patterns;
- and
- forming first via between the first lower metal line and the first upper metal line and second via between the second lower metal line and the second upper metal line using a third photomask manufactured based on the first and second via patterns.
Dependencies are inferred from the claim text.