Self-aligned three dimensional chip stack and method for making the same

A process of forming a self-aligned three dimensional vertical chip stack, comprising:

• forming a first scaffolding trench in an elastic and non-conductive scaffolding layer, the first scaffolding trench defined by a bottom surface have a width and sidewalls extending from the bottom surface to define a height;
• forming at least one additional elastic and non-conductive scaffolding trench in the first scaffolding trench, the at least one additional scaffolding trench having a width less than the first scaffolding trench width to define a stair therebetween;
• depositing a non-conductive adhesive liner in the at least one additional scaffolding trench and the first scaffolding trench;
• depositing a first chip in the first scaffolding trench, the first chip having a height less than the sidewall height of the first scaffolding height;
• depositing at least one additional chip in the at least one additional scaffolding trench, the at least one additional chip having a height less than the sidewall height of the at least one additional scaffolding height, wherein the at least one additional chip is vertically spaced apart from the first chip, and wherein the first chip and the at least one additional chip are each self-aligned within the first scaffolding trench and the at least one additional scaffolding trench, respectively.