Semiconductor package and manufacturing method of the same

A multiple-chip stacking structure, comprising

• a memory chip layer;
• a silicon-on-chip (SOC) layer connected to the memory chip layer by a first redistributed layer (RDL) and a through insulator via (TIV);
• and
• a ball grid array connected to the SOC layer through a second RDL,
• wherein the memory chip layer comprises a memory chip flip-chip bonded to the first RDL and surrounded by a solder.

A semiconductor package, comprising:

• a first layer, comprising:
• a first die structure,
• a solder disposed at the same level with the first die structure;
• and
• a first redistributed layer (RDL) under the first die structure, wherein an active region of the first die structure is electrically coupled to the solder through the first RDL;
• and
• a second layer, comprising:
• a second die structure, and
• a second redistributed layer (RDL) under the second die structure, wherein an active region of the second die structure is electrically connected to the active region of the first die structure through the first RDL and the second RDL.