Semiconductor package and fabrication method thereof
AssigneeMicron Technology, Inc.
InventorsShing-Yih Shih, Tieh-Chiang Wu
Life of this patent
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Abstract
A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. A redistribution layer (RDL) structure may be coupled to the first logic die, the second logic die, and the bridge memory die. The bridge memory die may be interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die ant the RDL structure. A molding compound may at least partially encapsulate the first logic die, the second logic die, and the bridge memory die.
Claims20
A semiconductor package, comprising:
- a first logic die;
- a second logic die located laterally adjacent to the first logic die, a first active face of the first logic die and a second active face of the second logic die facing a same direction;
- a bridge memory die coupled to both the first logic die and the second logic die on the first active face and the second active face;
- a redistribution layer (RDL) structure coupled to the first logic die, the second logic die, and the bridge memory die, wherein the bridge memory die is electrically coupled to the RDL structure by a plurality of through substrate vias extending from proximate the first active face and the second active face, through the bridge memory die, to the RDL structure, the bridge memory die being interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die ant the RDL structure;
- and
- a molding compound at least partially encapsulating the first logic die, the second logic die, and the bridge memory die.
A method of making a semiconductor package, comprising:
- coupling a bridge memory die a first logic die and a second logic die, the bridge memory die located on a first active face of the first logic die and a second active face of the second logic die, the first active fact facing a same direction as the second active face;
- at least partially encapsulating the first logic die, the second logic die, and the bridge memory die in a molding compound;
- and
- coupling a redistribution layer (RDL) structure to the first logic die, the second logic die, and the bridge memory die, wherein the bridge memory die is electrically coupled to the RDL structure by a plurality of through substrate vias extending from proximate the first active face and the second active face, through the bridge memory die, to the RDL structure, the bridge memory die being interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die ant the RDL structure.
Dependencies are inferred from the claim text.