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US 2017/0365533 A1Published application
Compact high-voltage semiconductor package
AssigneeInfineon Technologies Americas Corp.
InventorsEung San Cho, Chuan Cheah
Life of this patent
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Abstract
There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.
Claims11
1-10:
- (canceled)
11:
- A semiconductor package comprising:
- first and second power transistors;
- first and second drain contacts, first and second source contacts, and first and second gate contacts to provide respective external connections to said first and second power transistors;
- a first contour element formed between said first drain contact and said first source contact in said semiconductor package;
- a second contour element formed between said second drain contact and said second source contact in said semiconductor package;
- said first contour element increasing a first creepage distance between said first drain contact and said first source contact in said semiconductor package so as to increase a breakdown voltage of said semiconductor package;
- said second contour element increasing a second creepage distance between said second drain contact and said second source contact in said semiconductor package so as to increase said breakdown voltage of said semiconductor package.
4 more elements
12:
- The semiconductor package of claim 11, wherein at least one of said first contour element and said second contour element comprises a groove fanned in a packaging dielectric.
13:
- The semiconductor package of claim 11, wherein at least one of said first contour element and said second contour element comprises a ridge in a packaging dielectric.
14:
- The semiconductor package of claim 11, wherein said first and second power transistors are composite field-effect transistors (PETs) each including a group IV FET cascoded with a high-voltage (HV) group III-V transistor.
15:
- The semiconductor package of claim 11, wherein said first and second power transistors are coupled to form a half bridge, said first power transistor being a high side switch and said second power transistor being a low side switch of said half bridge.
16:
- A composite semiconductor package comprising:
- a first semiconductor package housing a first power transistor joined with a second semiconductor package housing a second power transistor;
- a first contour element formed between a first drain contact and a first source contact in said first semiconductor package;
- a second contour element formed adjacent a second drain contact in said second semiconductor package;
- said first contour element increasing a first creepage distance between said first drain contact and said first source contact in said first semiconductor package so as to increase a breakdown voltage of said composite semiconductor package;
- said second contour element increasing a second creepage distance in said second semiconductor package so as to increase said breakdown voltage of said composite semiconductor package;
- said first contour element interfacing with and mechanically engaging said second contour element.
4 more elements
17:
- The composite semiconductor package of claim 16, wherein at least one of said first contour element and said second contour element comprises a groove formed in a packaging dielectric.
18:
- The composite semiconductor package of claim 16, wherein at least one of said first contour element and said second contour element comprises a ridge in a packaging dielectric.
19:
- The composite semiconductor package of claim 16, wherein said first and second power transistors are composite field-effect transistors (FETs) each including a group IV FET cascaded with a high-voltage (HV) group III-V transistor.
20:
- The composite semiconductor package of claim 16, wherein said first and second power transistors are electrically coupled so as to provide a bidirectional switch.