Integrated circuit device and method of fabricating the same

An integrated circuit device comprising:

• a first fin-type active region in a first area of a substrate, the first fin-type active region protruding from the substrate and having a first channel region and a first recess;
• a first device isolation layer in the first area, the first device isolation layer covering both lower sidewalls of the first fin-type active region;
• a first gate line on the first device isolation layer, the first gate line covering the first channel region;
• a first source/drain region in the first recess;
• a second fin-type active region in a second area of the substrate, the second fin-type active region protruding from the substrate and having a second channel region and a second recess, the second area of the substrate being spaced apart from the first area of the substrate;
• a second device isolation layer in the second area, the second device isolation layer covering both lower sidewalls of the second fin-type active region;
• a second gate line on the second device isolation layer, the second gate line covering the second channel region;
• a second source/drain region in the second recess;
• and
• a fin insulating spacer only in the first area out of the first area and the second area, the fin insulating spacer covering both sidewalls of the first fin-type active region between the first device isolation layer and the first source/drain region.

An integrated circuit device comprising:

• a memory area, and a logic area connected to or spaced apart from the memory area;
• a first transistor comprising a first source/drain region filled in a first recessed portion of a first fin-type active region in the memory area;
• a first device isolation layer covering both lower sidewalls of the first fin-type active region in the memory area;
• a second transistor comprising a second source/drain region filled in a second recessed portion of a second fin-type active region in the logic area;
• a second device isolation layer covering both lower sidewalls of the second fin-type active region in the logic area;
• a first fin insulating spacer covering a first sidewall of the first fin-type active region between the first source/drain region and the first device isolation layer, the first fin insulating spacer having a first height;
• and
• a second fin insulating spacer covering a second sidewall of the second fin-type active region between the second source/drain region and the second device isolation layer, the second fin insulating spacer having a second height smaller than the first height, or no second fin insulating spacer covering the second sidewall of the second fin-type active region between the second source/drain region and the second device isolation layer.