Filling processes
AssigneeSamsung Electronics Co., Ltd.
InventorsJorge A. Kittl, Kyungseok Oh, Sung Min Kim
Life of this patent
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Abstract
A method of filling cavities in a semiconductor structure during fabrication. A layer of a first material, e.g., a polysilazane, is deposited on the semiconductor, and subjected to a first thermal process to change its chemical composition, e.g., to change it to silicon dioxide. It is then etched back, and the cycle of deposition, and thermal processing is repeated. The etch-back may also be repeated in one or more of the cycles after the first cycle, and a second thermal process, that may increase the density of one or more of the deposited layers, may be performed in one or more of the cycles.
Claims20
A method for filling a cavity in a semiconductor structure, the method comprising:
- forming a first layer of a first material in the cavity;
- subjecting the semiconductor structure to a first thermal process including subjecting the semiconductor structure to a temperature of at least 100° C. for interval of time;
- etching back the first layer to form a reduced first layer, having a reduced thickness;
- forming a second layer of a second material, in the cavity;
- and
- subjecting the semiconductor structure to a second thermal process including subjecting the semiconductor structure to a temperature of at least 100° C. for interval of time, to form, from at least the reduced first layer and the second layer, a single layer of uniform composition and density.
A method for filling a cavity in a semiconductor structure, the method comprising:
- forming a first layer of a first material in the cavity;
- subjecting the semiconductor structure to a first thermal process including subjecting the semiconductor structure to a temperature of at least 100° C. for interval of time, to form, from the first layer, a second layer of a second material having a chemical composition different from that of the first material;
- etching back the second layer to form a reduced second layer, having a reduced thickness;
- forming a third layer of a third material, in the cavity;
- and
- subjecting the semiconductor structure to a second thermal process including subjecting the semiconductor structure to a temperature of at least 100° C. for interval of time, to form from at least the reduced second layer and the third layer, a single layer of uniform composition and density.
A method for filling a cavity in a semiconductor structure, the method comprising:
- forming a first layer of a first material in the cavity;
- subjecting the semiconductor structure to a first thermal process including subjecting the semiconductor structure to a temperature of at least 100° C. for interval of time, to form, from the first layer, a second layer of a second material having a chemical composition different from that of the first material;
- etching back the second layer to form a reduced second layer, having a reduced thickness;
- forming a third layer of the first material, in the cavity;
- and
- subjecting the semiconductor structure to a second thermal process including an subjecting the semiconductor structure to a temperature of at least 100° C. for interval of time, to form from at least the reduced second layer and the third layer, a single layer, of uniform composition and density, of the second material.
Dependencies are inferred from the claim text.