Delayed equivalence identification

A method comprising:

• configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, wherein configuring the integrated circuit comprises force-enabling a pin of a clock gated circuitry to be Boolean TRUE;
• simulating N clock cycles in the circuit to provide performance results for one or more registers in the circuit, wherein N is a selected number of staging levels corresponding to a multi-level structural FANIN connection of the latches in the circuit;
• selecting one of the one or more registers;
• comparing the performance results for the selected register to performance results for each of the remaining registers to provide one or more equivalent delay candidate registers, wherein comparing the performance results for the selected register to performance results for each of the remaining registers includes determining whether each of the remaining registers is in a FANIN cone of the selected register;
• randomizing an initial state for the one or more equivalent delay candidate registers;
• and
• verifying that, for a register R whose input is D and whose output is Q, a check signal defined as Check=Next((D)̂Q) is always Boolean false to provide one or more confirmed equivalent delay registers.