Semiconductor memory devices, memory systems including the same and method of correcting errors in the same

A memory system comprising:

• at least one semiconductor memory device;
• and
• a memory controller configured to control the at least one semiconductor memory device, and to exchange main data with the at least one semiconductor memory device, wherein the at least one semiconductor memory device comprises,
• a memory cell array in which a plurality of memory cells are arranged, and
• an error correcting code (ECC) circuit configured to,
• generate parity data based on the main data,
• write a codeword including the main data and the parity data in the memory cell array,
• read the codeword from a selected memory cell row to generate syndromes, and
• correct errors in the read codeword on a per symbol basis based on the syndromes, the main data including first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row, the first data and the second data being assigned to one symbol of a plurality of symbols, the first memory cell and the second memory cell being adjacent to each other.